This application is related to Korean Application No. 2000-72090, filed Nov. 30, 2000, the disclosure of which is hereby incorporated herein by reference.
The present invention relates to integrated circuit devices and methods of fabricating the same and, more particularly, to integrated circuit devices having spin on glass (SOG) insulating layers and methods of fabricating the same.
As integrated circuit devices become more compact, the size of the elements within these devices gradually decrease and the devices tend to have more layers. The quantity of layers may cause problems in the integrated circuit device. For example, the aspect ratio of a contact hole may increase, via holes may penetrate a given region between the wires and/or the elements, the step coverage may be increased and the like. When the aspect ratio of the contact holes increase, it may become more difficult to form deep and narrow holes in certain layers of the device and to fill the narrow holes with conductive material to interconnect certain layers. Furthermore, a bad step coverage at the lower part of the device may result in a problem when the upper part of the device is patterned by means of a photolithography process to form the wires and/or the elements. Recently, a technique using an insulating layer has been developed that can reduce the frequency of these problems. For example, a method of utilizing this technique may include the steps of filling in gaps between the elements such as gate lines of the field effect transistor with an insulating layer, forming contact holes and pads in the insulating layer and planarizing the upper part of the insulating layer.
For example, a method of forming an insulating layer has been proposed including the steps of forming a boro-phospho silicate glass (BPSG) insulating layer and heating the BPSG layer at a high temperature of about 830xc2x0 C. In highly integrated circuit devices the width between gate lines is typically designed below a critical dimension (CD) of 0.2 xcexcm. Thus, the high temperature heat treatment discussed above may damage the elements, for example, transistors in the integrated circuit device. Thus, another method proposed the use of an O3 tetra ethyl ortho silicate undoped silicate glass (O3xe2x80x94TEOS USG), or high density plasma (HDP) oxide layer to address the problem with respect to high temperatures. However, these layers may cause voids or seams in the integrated circuit device when the width between gate lines of the field effect transistor is designed below a CD of 0.2 xcexcm, for example, about 0.18 xcexcm.
Accordingly, another method using a spin on glass (SOG) layer as an insulating layer has been developed. SOG material is a good material to use to fill gaps between the gate lines and to reduce the step coverage since it also has a liquid state (spin on liquid (SOL)). Once the SOG material is applied to a substrate, the SOG material is subjected to a soft bake process at a low temperature of from about 75xc2x0 C. to about 300xc2x0 C. to remove solvent ingredients, such as dialkyl ether. The soft bake process may be followed by a hard bake process at a temperature of about 400xc2x0 C. to obtain a finished SOG insulating layer. A curing process may also be performed by annealing the SOG material at a temperature of more than about 700xc2x0 C. to remove unstable ingredients in the SOG layer and to stabilize crystallized structures therein.
However, the curing process may not completely remove all impurities, such as organic elements, hydrogen, nitrogen, inorganic elements etc., thus, the remaining impurities may remain in the SOG layer and may cause layer characteristics to deteriorate. The deterioration in layer characteristics may cause the formation of contaminants and crystallized structures in subsequent processes. Since curing begins on the surface of the SOG layer, lower parts of the SOG layers and corners between the gate lines typically contain more left over impurities.
Furthermore, if a SOG layer containing impurities is subjected to an etch process and a cleaning process, the etch rate with respect to the regions of the SOG layer containing impurities may be higher than the etch rate with respect to regions of the SOG layer that are free of impurities. Generally, crystallized structures in the SOG layer are transformed into porous crystallized structures by means of impurities.
Typically, a SOG layer that contains porous crystallized structures has a very high wet etch rate. Also, the portions of the SOG layer containing impurities may have different characteristics with respect to thermal expansion which may cause elements in the integrated circuit device to deteriorate, thus producing more devices of inferior quality.
For example, the case of an inorganic SOG insulating layer will be described.
An inorganic SOG insulating layer may comprise materials such as hydro silsesquixoxane (HSQ) or polysilazane. The SOG insulating layer may be formed after forming a metal oxide silicon (MOS) or other field effect transistor structure on a substrate. As discussed above, a porous crystallized structure portion is typically formed at the lower part of the SOG insulating layer between the gate lines. Thus, when pads for bit line contacts or storage node contacts are formed by means of a self-aligned method, for example, a self aligned contact (SAC) technique, the lower part of the SOG layer having porous crystallized structures may be exposed. The exposed lower part of the SOG layer may be easily etched using an etchant such as a mixture of NH4OH, H2O2, and de-ionized water called SCl, or buffered oxide etcher (BOE). Accordingly, pipe line shaped bridges can be formed between the adjacent pads through the exposed lower part of the SOG layer. These bridges may cause short circuits between wires of the integrated circuit device, which may cause the integrated circuit device to function abnormally.
FIG. 1 and FIG. 2 are side cross-sectional views of a portion of a substrate of a conventional integrated circuit device. Now referring to FIG. 1, gate lines are formed on the substrate 10 on which an isolation layer 11 is formed. The gate lines are formed by depositing and patterning a gate insulating layer 13, a conductive layer 15, and a silicon nitride capping layer 17 in order. On sidewalls of the gate lines, spacers 19 are formed from a silicon nitride layer. An optional liner layer (not shown) may be deposited, and a polysilazane SOG layer 21 may be formed by using a spin coating method. Thereafter, a bake and an annealing process are performed. Now referring to FIG. 2, a cross-section between gate lines of a portion of the substrate along line A-Axe2x80x2 shown in FIG. 1 is shown. A portion of the SOG layer below the dotted line in FIG. 2 represents a portion of the SOG layer that contains impurities, i.e. a portion of the SOG layer that is incompletely cured during the annealing process.
Now referring to FIG. 3, a cross-section of the substrate of FIG. 2 on which contact holes are formed in the SOG insulating layer and filled with polysilicon material will be described. After the annealing process, contact holes 23 are formed to form storage node contact pads and bit line contact pads by means of a self-aligned method. After the contact holes 23 are formed, a cleaning process is carried out and the contact holes 23 are filled with a polysilicon layer by means of a chemical vapor deposition (CVD) method. Thereafter, a chemical-mechanical polishing (CMP) or an etch back process may be performed to divide pads. However, in the cleaning process, the SOG layer between the contact holes may be partially etched to form irregular side surfaces as shown in FIG. 3. In some situations, a portion of the SOG layer 21 may be pierced and the polysilicon layer may be deposited in the pierced portion of the SOG layer 21. This situation may cause a short circuit between the bit line contact pads and the adjacent storage node contact pads.
Embodiments of the present invention provide methods of fabricating integrated circuit devices including the steps of forming a spin on glass (SOG) insulating layer on an integrated circuit substrate, the SOG insulating layer including sidewalls that define contact holes therein and forming spacers on the sidewalls of the SOG insulating layer.
In some embodiments of the present invention forming a SOG insulating layer includes the steps of spin coating a SOG material on the surface of the substrate, baking the SOG material, and annealing the SOG material. The SOG material may include at least one of polysilazane and silsesquioxane. Baking the SOG material may include the step of baking the SOG material at a temperature of about 400xc2x0 C. for several minutes. Annealing the SOG material may include the step of annealing the SOG material at a temperature of from about 350xc2x0 C. to about 850xc2x0 C. for from about 10 minutes to about 2 hours. Annealing the SOG material may alternatively include the step of annealing the SOG material at a temperature of about 700xc2x0 C. to about 800xc2x0 C.
Other embodiments of the present invention include the steps of forming a photoresist pattern on the integrated circuit substrate and dry-etching the SOG layer using the photoresist pattern as a mask in between forming the SOG insulating layer and forming the spacers.
In further embodiments of the present invention forming spacers on sidewalls of SOG insulating layer may include the steps of forming a spacer layer on the surface of the integrated circuit substrate and etching the spacer layer to form the spacers on the sidewalls of the contact holes. The spacer layer may include at least one of a high temperature oxide (HTO), a medium temperature oxide (MTO) and a silicon nitride (SixNy). The spacer layer may have a thickness of from about 50 xc3x85 to about 400 xc3x85. Alternatively, the spacer layer may have a thickness of from about 100 xc3x85 to about 200 xc3x85.
Still further embodiments of the present invention may include the steps of cleaning the integrated circuit substrate and depositing a conductive material in the contact holes to form a conductive layer. Cleaning the surface of the substrate may include the step of performing a wet etch over the whole surface of the integrated circuit substrate for about 10 minutes. Performing the wet etch may include a wet cleaning process using a mixture of NH4OH, H2O2 and de-ionized water (SCl). Depositing a conductive material may include forming a conductive layer using a CVD process. The conductive layer may be a polysilicon conductive layer. The method of the present invention may further include performing a CMP process to expose an upper surface of the SOG insulating layer.
Some embodiments of the present invention provide an integrated circuit device including an integrated circuit substrate, a spin on glass (SOG) insulating layer on the integrated circuit substrate, the SOG insulating layer including sidewalls that define contact holes therein and spacers on sidewalls of the SOG insulating layer.